A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
The present invention disclosed herein relates generally to electronic testing systems and methods. More particularly, the present invention relates to a system and method for testing an integrated circuit (IC) device using an FFT algorithm, supported by a non-iterative FFT coherency analysis algorithm which establishes FFT sample-set coherency, to analyze an output signal generated by IC the device in response to an input test signal supplied thereto.
When an integrated circuit (IC) is tested for proper operation, a test signal is typically supplied at its input. The output signal from the IC is then analyzed to determine what effects, if any, the IC had on the input test signal. The analysis of the output signal is performed using a Fast Fourier Transform (FFT) for which a mathematical relationship involving four numbers must fulfill a certain inter-relationship, thereby establishing FFT sample-set coherency. These four numbers are as follows: test frequency, sample frequency, the number of samples, and the number of periodic cycles over which the samples were taken.
Currently, a best-guess iterative process is used to determine a xe2x80x9cvalidxe2x80x9d set of four numbers, properly related. That is, one may start with one given and up to three approximated values. The interrelationships of these values are then analyzed. It is very unlikely that the results of the analysis will be satisfactory. Typically, one or more numbers must be changed, and the results re-analyzed. The current methodology of finding proper testing parameters are time consuming and inefficient.
A need therefore exists,for a system and method that overcome the above, as well as other, disadvantages of the conventional IC device testing procedure.
It is an object of the present invention to provide a system and method for testing IC devices.
It is another object of the present invention to provide a system and method for testing IC devices using an FFT algorithm supported by a non-iterative FFT coherency analysis algorithm which establishes FFT sample-set coherency.
It is still another object of the present invention to provide a system and method for testing IC devices using an FFT algorithm supported by a non-iterative FFT coherency analysis algorithm to analyze an output signal generated by the IC device in response to an input test signal supplied thereto.
The above and other objects are achieved by a method for testing an integrated circuit (IC) device using an FFT algorithm, supported by a non-iterative Fast Fourier Transform (FFT) coherency analysis algorithm, which establishes FFT sample-set coherency. According to the inventive method, a test signal of a predetermined test frequency is generated. The test signal is supplied to the IC device. A sample frequency is selected for sampling the test signal which is output from the IC device. A number of samples is then selected from the sampled test signal. A number of periodic cycles over which the samples have been taken is selected such that the predetermined test frequency, sample frequency, number of samples and number of periodic cycles are related to each other by a predetermined relationship.
In accordance with one aspect of the present invention, the number of samples and the number of periodic cycles are relatively prime.
In accordance with another aspect of the present invention, the sample frequency is selected as an approximate value, and the sample frequency is further calculated as an exact value which is a function of the predetermined test frequency, the number of samples and the number of periodic cycles.